A 10-bit Charge-Redistribution ADC Consuming 1.9 μW at 1 MS/s

This paper presents a 10 bit successive approximation ADC in 65 nm CMOS that benefits from technology scaling. It meets extremely low power requirements by using a charge-redistribution DAC that uses step-wise charging, a dynamic two-stage comparator and a delay-line-based controller. The ADC requires no external reference current and uses only one external supply voltage of 1.0 V to 1.3 V. Its supply current is proportional to the sample rate (only dynamic power consumption). The ADC uses a chip area of approximately 115--225 μm2. At a sample rate of 1 MS/s and a supply voltage of 1.0 V, the 10 bit ADC consumes 1.9 μW and achieves an energy efficiency of 4.4 fJ/conversion-step

A 10-bit Charge-Redistribution ADC Consuming 1.9 μW at 1 MS/s

This paper presents a 10 bit successive approximation ADC in 65 nm CMOS that benefits from technology scaling. It meets extremely low power requirements by using a charge-redistribution DAC that uses step-wise charging, a dynamic two-stage comparator and a delay-line-based controller. The ADC requires no external reference current and uses only one external supply voltage of 1.0 V to 1.3 V. Its supply current is proportional to the sample rate (only dynamic power consumption). The ADC uses a chip area of approximately 115--225 μm2. At a sample rate of 1 MS/s and a supply voltage of 1.0 V, the 10 bit ADC consumes 1.9 μW and achieves an energy efficiency of 4.4 fJ/conversion-step

Nanopower SAR ADCs with Reference Voltage Generation

This chapter targets low-power techniques for nanopower SAR ADCs with reference voltage generation. First of all, a 106nW 10b 80 kS/s SAR ADC with duty-cycled reference generation is presented, where a CMOS voltage reference, a duty-cycling block, and a LDO are integrated with the SAR ADC together. Furthermore, a low-power bidirectional comparator is utilized in the SAR ADC to reduce the power consumption. The reference-included SAR ADC achieves a FoM of 2.4fJ/conv.-step. Second, an energy-free DAC reset technique, “swap-to-reset,” is presented to deal with the large DAC reset energy in a SAR ADC, which is usually large compared with DAC conversion energy. In the prototype, the DAC energy consumption is reduced by one-third with “swap-to-reset” applied to the 2 MSBs. Finally, a low-power and area-efficient discrete-time reference driver is introduced. By calculating the energy consumption of each switching step, the DAC in a SAR ADC can be driven by a pre-charged decoupling capacitor compensated by a small auxiliary DAC. In the prototype, the SNDR/SFDR are improved by 2.7 dB/11.6 dB after enabling the 3b DAC compensation and the discrete-time reference driver only adds 10.8% and 10.1% to the power and chip area of the SAR ADC, respectively.</p